1. Field of the Invention
The present invention generally relates to a semiconductor device and a method for fabricating the same, and more particularly, to a gate structure and a method for fabricating the same, and a method for fabricating a memory.
2. Description of Related Art
Currently, memory cells are often fabricated together with their peripheral circuits in order to shorten the processing time and to simplify the processing process. Furthermore, transistors having certain characteristic functions are often respectively formed in the memory cell area and the peripheral circuit area, according to the functions required in the device. Specifically, transistors of a dynamic random access memory (DRAM) include transistors in the memory cell area and transistors in the peripheral circuit area.
Typical transistors in a conventional memory cell area have a stack type gate structure. When circuits become more integrated and dimension of the device become smaller and smaller, channels of the transistors thereof are shortened accordingly. Such shortened channels often cause short channel effect (SCE). In order to resolve the SCE problem, a recess channel process is often conducted to elongate the length of the channel, and thus reducing the SCE and the leakage current thereof. Typically, a recess channel process often includes steps of: forming a recess in a substrate, forming a conformal gate oxide layer in the recess, forming a conductive layer to cover the gate oxide layer and fill the recess, and performing a patterning process to define a gate structure. Typically, the foregoing patterning process include: covering an area in which the gate structure is to be formed later with a patterning photo-resistant layer; and removing the conductive layer which is uncovered by the patterning photo-resistant layer. However, in the foregoing conventional recess channel process, an alignment error often exists between the patterning photo-resistant layer and the conductive layer. Therefore, it is hard to correctly define the gate structure.
Further, typical transistors in a conventional peripheral circuit area are complementary metal oxide semiconductor (CMOS) transistors, including N-type CMOS (NMOS) transistors, and P-type CMOS (PMOS) transistors. In more concentrated integrated circuit and smaller devices, PMOS transistors are more likely to cause SCE. In order to resolve this problem, a metal gate process is often performed to replace a poly-silicon gate with a metal gate. However, the metal gate process brings problems of poor thermal stability and undesired gate dopant diffusion.
Accordingly, it is an important concern to avoid the above problems and produce high-quality devices.